Title: Multithreaded 32 bit RISC implementation in FPGA


Abstract: The design of a 32 bit RISC multithreaded core, developed during the TEIS2012 VHDL course, is described.

The CPU core implements a three stage pipeline with a true single cycle instruction set, with the decoder automatically generated from a database. Fine-grained multithreading is implemented, allowing the core to switch thread every clock cycle.

A validation environment using an Nios II processor and VGA screen is described.

This shows the internals of the CPU after each instruction.

Ulf Samuelsson, AGSTU School of Higher Vocational Education, Sweden