Title: 10 Ways to Effectively Debug your FPGA Design


Abstract: Today’s FPGAs implement the equivalent of millions of ASIC gates. When the design fails to synthesize or fails to operate as expected on the board,the designer is faced with the daunting task of determining the source of the failure among potentially thousands of input files. Given how lengthy design iteration runtimes have become,designers have an enormous need for better ways to find errors early, incrementally and en masse. This paper is an elaboration of state of the art debug tools and techniques that avail today’s high-end FPGA designers.


Antti Innamaa, Synopsys, USA